Genie BIOS Settings:
FSB Bus Frequency - 300
AGP Bus Frequency - 67mhz
Clock Spread Spectrum - Disabled
LDT Downstream Width - Auto
LDT Upstream Width - Auto
LDT/FSB Frequency - x2
CPU/FSB Frequency Ratio - 8x
K8 Cool 'n' Quiet Support - Disable
CPU VID Control - xx
CPU VID Special Control - Above VID * xx
Chip Set Voltage Control - 1.90v
AGP Voltage Control - 1.60v
DRAM Voltage Control - 3.10v
DRAM Configuration:
DRAM Frequency Set - 200 (DRAM/FSB:1/1)
Command Per Clock (CPC) - Enable
CAS Latency Control (Tcl) - 2.5
RAS# to CAS# delay (Trcd) - 04 Bus Clocks
Min RAS# active time (Tras) - 7 Bus Clocks
Row precharge time (Trp) - 03 Bus Clocks
Row Cycle time (Trc) - 07 Bus Clocks ---> 9-10
Row refresh cyc time (Trfc) - 14 Bus Clocks -->16
Row to Row delay (Trrd) - 03 Bus Clocks
Write recovery time (Twr) - 03 Bus Clocks
Write to Read delay (Twtr) - 02 Bus Clocks
Read to Write delay (Trwt) - 03 Bus Clocks
Refresh Period (Tref) - 4708 Cycles --> 3072
Write CAS Latency (Twcl) - Auto --> 1
DRAM Bank Interleave - Enabled
DQS Skew Control - Increase --> decrease
DQS Skew Value - 0 --> 128
DRAM Drive Strength - Level 1 --> try 1 3 5 7
DRAM Data Drive Strength - Auto --> try 1 or 2
Max Async Latency - 8.0ns
Read Preamble Time - 6.0ns
IdleCycle Limit - 128 Cycles --> 256
Dynamic Counter - Disable
R/W Queue Bypass - 16 x --> 8x
Bypass Max - 07 x --> 4x
32 Byte Granularity - Disable(8 Bursts)
TCCD/TCC5 discussions, memory tuning, voltage, etc.
Aug 24 2005, 02:46 AM
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