if you can't pass the actual rating, send it for RMA

memtest86 is not unreliable. it's meant to test purely on ram.

you can pass memtest86 but fail to get into windows because other factor counts... like cpu stability and other components as well

Yes, there are some TCCD that cannot do 2-2-2-x 200mhz @1T, because TCCD is actually binned to run at 500mhz

same case with TCC5, which is actually binned at 466mhz, but results showing that more/most TCC5 can do 2-2-2-x 200mhz compare to TCCD

I run memtest with test #5 until it's fully stable without errors for hours.

Then I start playing with vcore, vchipset and vagp if it's not stable in windows. The method works quite well.

TCC5 is actually the same chip of TCCD ... which is the Rev.F

It's just binned at lower speed to reduce manufacturing cost.... but technically, they're the same thing.

now I'm currently doing 300mhz 2.5-4-3-7-1T with only 2.7Vdimm after some fine tuning on the extra memory settings on DFI... but not totally perfect, got 6 errors for 200loops.

EDIT : with Idle Cycle Clock set to 64 Cycles, currently passing 300loops without any error

This post has been edited by soulfly: Sep 25 2005, 01:51 AM

system:
AMD Sempron 64 2800+ "Rev. E6" LBBLE 0527EPAW
DFI LP UT nF3 250Gb (Bios 5/4)
1x 512MB OCZ EL PC-3200 Platinum Rev.2 1.1 (TCC5)

Genie BIOS Settings:

FSB Bus Frequency - 300
AGP Bus Frequency - 66mhz
Clock Spread Spectrum - Disabled
LDT Downstream Width - Auto
LDT Upstream Width - Auto
LDT/FSB Frequency - Auto
CPU/FSB Frequency Ratio - Auto


CPU VID Control - Auto
CPU VID Special Control - Auto
Chip Set Voltage Control - 1.60v
AGP Voltage Control - 1.50v
DRAM Voltage Control - 2.70v

DRAM Configuration Settings:

DRAM Frequency Set - 200 (DRAM/FSB:1/10)
Command Per Clock (CPC) - Enable
CAS Latency Control (Tcl) - 2.5
RAS# to CAS# delay (Trcd) - 04 Bus Clocks
Min RAS# active time (Tras) - 07 Bus Clocks
Row precharge time (Trp) - 03 Bus Clocks
Row Cycle time (Trc) - 07 Bus Clocks
Row refresh cyc time (Trfc) - 14 Bus Clocks
Row to Row delay (Trrd) - 02 Bus Clocks
Write recovery time (Twr) - 02 Bus Clocks
Write to Read delay (Twtr) - 02 Bus Clocks
Read to Write delay (Trwt) - 02 Bus Clocks
Refresh Period (Tref) - 4708 Cycles
Write CAS Latency (Twcl) - 1
DRAM Bank Interleave - Enabled



DQS Skew Control - Increase Skew
DQS Skew Value - 64
DRAM Drive Strength - Level 1
Max Async Latency - 07.0 Nano Seconds
Read Preamble Time - 05.0 Nano Seconds
IdleCycle Limit - 64 Cycles
Dynamic Counter - Disable
R/W Queue Bypass - 16x
Bypass Max - 07 x
32 Byte Granularity - Disable(8 Bursts)



some screenies .....


This post has been edited by soulfly: Sep 25 2005, 12:58 PM

now trying to run with divider... but unluckily the setting that i used for 1:1 is not applicable

actually i'm trying to run at 9/10 (300mhz ram, 338mhz htt) since i know my processor is capable of running at 2.7ghz stable. but seems like the ram need different memory setting. 2.8vdimm also no luck... maybe need 2.9vdimm.

EDITED: result : success

I played around with :
Max Async Latency
Read Preamble Time
IdleCycle Limit

These values should be affected/connected to divider and htt. Then I bump the voltage to 2.8V..... now can get more than 3 hrs memtest stable... and hopefully it's really stable for SuperPi 32M and prime

will post the screenie and setting afterwards after some more testing.

This post has been edited by soulfly: Sep 26 2005, 08:23 PM

RMA is only possible if your RAM does not meet its default SPD rating.

try use memtest86 to check whether it's your ram problem or your setting problem.

you can only RMA if the stick cannot do what is rated by the manufacturer. if only 1 stick problem... both should be returned (if it's a dual channel kit).

have u fine tuned the memory timings?

your cpu/mobo?

if u're quite sure that your proc is limited to only 245mhz fsb... so BH is a good choice then.

A lot of TCCD can do 300mhz 2.5-3-3-7 provide that u fine tune the ram and enuff voltage supplied.

my TCC5 does not run 300mhz at 2.5-3-3-7 ... it can only run at 2.5-4-3-7 with 2.7Vdimm only, if the HTT is 300mhz

if using 'divider', it needs 2.8Vdimm

yes... coz basically it's the same chip

does nF3 Ultra and nF3 250Gb has the same genie/memory bios structure? if yes... i can share mine. but i know nF4 is different.

I suggest that you loosen some values such as

Twr = 3
Trrd = 3
Trc = 7/12
Trfc = 14/16
Twtr = 2
Trwt = 3
Tref = 4078
Twcl = Auto/1
Write Cas Latency (Twcl) = 1
Max Asynchronous Latency = 8
Read Preamble = 5.0/5.5/6.0
Dynamic Idle Cycle Limit = disable
DDR Output Driving = Weak Drive

no off topic please

try this....

Trc = 12
Trfc = 16
Twr = 2
Twtr = 2
Trwt = 2
Tref = 4078
Twcl = 1

Read preamble = 5ns
Async lantecy = 7ns

But I guess... it's pretty much the same like other common DFI nF4/TCCD settings