QUOTE(clawhammer @ Dec 4 2007, 04:57 PM)
Ok, perhaps this is what termed as "FSB wall"

I guess in this case, things are a lot different between AMD and Intels.
Added on December 4, 2007, 4:58 pmThis can be determined to the FSB:DRAM ratio in the BIOS?
Er.. IINM the ratio just tells stuff when to wait and when not to wait. 5:6 just means that the processor gets five "slices" of time, while the RAM gets 6. This means that after the 5th slice, the RAM is ready but the proc is not. So the RAM has to wait for the proc to finish doing the fifth slice before it can continue. The fact that the RAM has to wait a bit for the fifth slice results in a slightly higher latency (ie. the RAM is slightly faster than the proc, so it's sitting there doing nothing while the proc is finishing up the previous "slice".) If you run 1:1, no one has to wait, the give and take becomes very smooth.
This guy has a better explanation :
QUOTE
One of the jobs of the memory controller is to resynchronize the information it receives from the CPU. It delays whichever information is received first until the other arrives. The amount of delay is called "setup/hold time." It accomplishes this by sending the earlier received data on an electronic run-around-the-block called a "feedback loop." The hope is that by the time the first data has returned from its delaying run, the other paired data will have arrived.
From
http://www.overclock.net/faqs/119265-how-c...-save-your.htmlOkay think of it this way, you know clocks. They go tick-tock, tick-tock, tick-tock. You always have a pair. What you're doing with 5:6 is setting up the system so that for a set period of time, you have 5 ticks and 6 tocks. So it goes tick-tock, tick-tock, tick-tock, tick-tock, tick-tock, tock. Notice the last one's missing a "tick". That's because the processor hasn't produced it yet. So the last tock has to wait for the last tick before it can continue. It can't go "tock" until the processor goes "tick". The next tick that comes along is paired with the last tock and the system runs smoothly again, until the next fifth tock. That explains why there's a bit of added latency there. I believe this is what they mean by "asynchronous".
The thing is that, clocks can't wait. They run at a set frequency, and whether or not anything gets done it still runs at that frequency. So if the clock runs at 500 Mhz 5:6, it still runs at 500 Mhz, it's just that it's inefficient, because a lot of the time the RAM is doing the PC equivalent of shuffling papers and looking busy.
If you run at 1:1 it's synchronous, so the clock runs like, er, clockwork

so there's no wait time, and thus less latency.
I don't know if any of this is true, it's just what I understand